{circle around (1)} Japanese Patent Laying Open No. 2002-261014 “method of making nitride semiconductor devices” proposes a method of making LDs by the steps of preparing a foreign material (e.g., sapphire) substrate of a thickness more than 3 mm, growing an InGaN buffer layer of a thickness less than 0.3 μm on the sapphire substrate, growing an over-100 μm thick GaN crystal on the buffer layer, obtaining a GaN substrate by eliminating the sapphire substrate (wafer), piling thin epitaxial layers on the GaN substrate, dividing the GaN wafer into LED device chips and producing LED devices.
The method of {circle around (1)} produces an epitaxial GaN wafer (substrate) by preparing a sapphire (Al2O3) or spinel (MgAl2O4) wafer, making a buffer layer on the wafer, growing a thin GaN layer on the buffered layer, eliminating the sapphire wafer by polishing, obtaining an independent GaN substrate (as-cut wafer), polishing the as-cut GaN wafer into a mirror GaN wafer, piling epitaxially a GaN buffer layer, a crack-preventing layer, an n-cladding layer, an n-photoguide layer, an active layer, a p-capping layer, a p-photoguide layer, a p-cladding layer and a p-contact layer in order on the GaN wafer. Every unit on the wafer is shaped into a ridge shape by etching away both sides of the p-type layers. Further n-electrodes and p-electrodes are formed on an exposed n-layer and a top p-layer of the device units on the wafer respectively. The processed wafer is scribed along lengthwise and crosswise boundaries of the units and is divided mechanically into individual device chips. The method requires two polishing steps and one mechanical chip-separation step.
{circle around (2)} Japanese Patent Laying Open No. 11-001399, “method of producing gallium nitride semiconductor single crystal substrate and gallium nitride diodes utilizing the substrate”, proposes a GaN substrate producing method by growing a thick GaN film on a sapphire wafer, removing the sapphire wafer by polishing, obtaining an GaN substrate, growing a thick GaN film on the GaN wafer, polishing surfaces of the GaN crystal substrate and obtaining a GaN mirror wafer. The method {circle around (2)} requires two polishing steps, one is for eliminating the sapphire wafer and the other is for making a GaN mirror wafer. When device units are made by piling n-type and p-type InGaN, AlGaN and GaN films on the GaN wafer, the device units should be separated from each other by scribing and dividing the processed wafer into device units by mechanical methods of using cutlery. The divided device units are called “chips”. The chip is composed of a thick substrate (a part of the wafer) and thin epitaxial films grown on the substrate. The substrate occupies most of the volume of a chip. {circle around (3)} Japanese Patent Laying Open No. 2003-165799 and {circle around (4)} Japanese Patent Laying Open No. 2003-183100 have no direct relation with a method of producing nitride semiconductor devices. Thus {circle around (3)} and {circle around (4)} are not the nearest prior art to the present invention. However, {circle around (3)} and {circle around (4)} work an important role in the present invention. Thus {circle around (3)} and {circle around (4)} are now clarified.
{circle around (3)} Japanese Patent Laying Open No. 2003-165799 discloses a new method of producing a GaN substrate contrived by the same Inventors as the present invention. {circle around (3)} gives a basic technique of making a GaN substrate which acts as an important starting wafer in the present invention. {circle around (3)} is clarified by referring to FIGS. 1-10. Isolated mask dots M (SiO2, SiN, W, Pt, etc.) are allotted on an undersubstrate US (GaAs, SiC, sapphire, spinel single crystal etc.) as shown in FIG. 1. A surface of the undersubstrate US is divided into me aryask-covered parts and an exposed part. FIG. 7 is a sectional view of the same masked undersubstrate. Vapor phase growth produces a GaN crystal on the masked undersubstrate US. The mask has a function of suppressing growth. GaN growth starts only on the exposed part of the undersubstrate US. The mask dots delay crystal growth and form holes as shown in FIG. 2 and FIG. 3. Bottoms of the holes coincide with the mask dots. The holes are composed of several slanting walls. The slanting walls are facets F. Thus the holes are called “facet pits”.
FIG. 8 is a sectional view of facet pits appearing in FIGS. 2 and 3. Facets F build hexagon cone pits or dodecagon cone pits above the isolated mask dots M. FIGS. 2 and 3 demonstrate the formation of simpler hexagon cone pits on dot masks M. No pit happens on an exposed part without mask dots. Maintaining the facet pits, {circle around (3)} and {circle around (4)} grow GaN on the masked undersubstrate without burying facet pits till the end of the growth. The facet-maintaining growth is called a “facet growth”. FIG. 2 and FIG. 3 are different in the directions of the facets constructing the pits. Both facet pits shown by FIG. 2 and FIG. 3 can be prepared by adjusting growing conditions and determining a direction of the mask dot alignment on the undersubstrate. Dislocations D extend in directions perpendicular to a growing surface. Dislocations D on the facets move inward in the facet pits, and fall to the bottoms of the facet pits during the facet growth. Pit bottoms gather and arrest dislocations D. FIG. 9 is a section showing the growing GaN crystal with facets and pits. The parts which accumulate and accommodate many dislocations are called “defect accumulating regions H” on the masks M.
Other parts except H become low defect density single crystals. The parts below the facets on the exposed parts are called “low defect density single crystal regions Z”, which have high electric conductivity. When the growing crystal is not fully covered with facets and is partially covered with C-planes, the parts growing under the C-planes are called “C-plane growth regions Y”, which are low defect density single crystal regions of low electric conductivity. The C-plane growth regions Y should be discriminated from Z. Thus the parts are called the C-plane growth regions Y. Then the mask dots M are covered with the defect accumulating regions H as shown in FIG. 9. In the best case, the crystal growth proceeds on the facetted state shown in FIG. 4, in which facet pits are nearly in contact with each other.
When the crystal grows up to a sufficient height, the growth is finished. The grown crystal sample is taken out of a furnace. The facetted, rugged surface is eliminated by polishing. The undersubstrate is removed by grinding, etching or polishing. A flat, smooth freestanding GaN substrate (wafer) is obtained. FIG. 5 shows a plan view of the structure of the freestanding GaN wafer. FIG. 10 denotes a section of the same GaN wafer. The GaN wafer is not homogeneous but inhomogeneous. The GaN wafer (substrate) is composed of defect accumulating regions H, low defect density single crystal regions Z and C-plane growth regions Y arranged in a concentric relation. The GaN wafer is transparent, so that human eye sight cannot discriminate between the regions H, Z and Y. Cathode luminescence (CL) can clarify the structure composed of H, Z and Y. The growing method of {circle around (3)} is called “dot-type facet growth method”, since the mask dots M and the defect accumulating regions H are distributed as isolated, separated points. The defect accumulating region H is only an isolated point without patterning a closed loop.
Both the low defect density single crystal regions Z and the C-plane growth regions Y are single crystals of low defect density with the common orientation. Both Z and Y are collectively called “low defect density regions ZY” in the present invention. When the crystal has no C-plane growth region Y, the GaN crystal is only composed of H and Z as demonstrated by FIG. 6. In this case, the collective ZY includes only Z.
{circle around (4)} Japanese Patent Laying Open NO. 2003-183100 proposes another new method of producing gallium nitride substrates invented by the same inventors as the present invention. The new method forms mask stripes M on an undersubstrate US as shown in FIG. 11 and grows gallium nitride in vapor phase on the stripe masked undersubstrate US. The method is called a “stripe facet growth method”. The mask has a function of suppressing crystal growth. The mask stripes M prevent GaN from growing thereon. Exposed parts between stripes promote growth. Grown crystals on the exposed parts make facets F and F on both sides. The stripes produce facet grooves formed with facing facets. GaN is grown on the masked undersubstrate by maintaining the facets and the grooves till the end. The facets convey dislocations into the facet groove bottoms. The groove bottoms arrest and accommodate dislocations.
FIG. 12 demonstrates such a function of the facets that the dislocations are conveyed to the facet grooves upon the stripes M. Dislocations D assemble on the mask stripes M. The stripes M are fully covered with dislocation-gathering crystals. The on-mask parts into which dislocations are converging are called “defect accumulating regions H”. The defect accumulating regions H deprive the other parts of dislocations D. The other parts, which lose dislocations D, become low dislocation density regions, which are classified into two different regions. The regions growing under the facets F on the exposed parts are called “low defect density single crystal regions Z”, and the other regions growing under C-plane on the exposed parts are called “C-plane growth regions Y”, which are also low defect density single crystals. Y is different from Z in electric conductivity, although Z and Y are both low defect density single crystals. Y has low electric conductivity, and Z has high electric conductivity. When the GaN crystal is grown to a sufficient thickness, the growth is ended and the GaN crystal is taken out of a furnace. The GaN crystal has a rugged surface with facets. The facetted rugged surface is eliminated by polishing. A smooth surface GaN/undersubstrate is produced. Then the undersubstrate US is removed by polishing or etching. A smooth surfaced freestanding GaN substrate is obtained.
FIGS. 13 and 14 demonstrate final, flat, freestanding GaN substrates (wafers). FIG. 13 shows a GaN substrate (wafer) of an HZYZH structure with C-plane growth regions Y. FIG. 14 shows a GaN substrate (wafer) of an HZH structure without C-plane growth region Y. Appearance or disappearance of C-plane regions Y can be chosen by controlling the widths of the facets F in the stripe facet method. The growing method is called a stripe facet method, since the arrangements of the masks and the defect accumulating regions H are sets of parallel straight lines. In the stripe facet method, the defect accumulating regions H are isolated, straight, parallel and open lines. An open line means that the line has two open ends. At the point, the stripe facet method is different from the present invention, which proposes a set of closed loop H.
The low defect density single crystal regions Z and the C-plane growth regions Y are low dislocation density single crystals having the common crystal orientation. Then sometimes Z and Y are collectively called as low defect density regions “ZY” in the present invention. As explained hitherto, the dotted defect accumulating regions H in the dot facet method {circle around (3)} are isolated points, which are zero-dimension points, and are not closed loops. The striped defect accumulating regions H in the stripe facet method {circle around (4)} are isolated, parallel, straight lines, which are one-dimension lines, and are not closed loops.
Neither dot facet nor stripe facet methods, which make isolated or open line defect accumulating regions H, can serve undersubstrates which is applied to the present invention. However, the dot and stripe facet methods have been explained in detail, because these facet growth methods give the foundation of the present invention.